This invention relates to arrays of memory cells and, more particularly, to techniques for erasing such arrays.
Erasable programmable read-only memory ("EPROM") technology is well known for use in both memory and programmable logic applications. In particular, EPROMs are implemented using floating gate field effect transistors in which the binary states of the EPROM cell are represented by the presence or absence on the floating gate of sufficient charge to prevent conduction even when a normal high signal is applied to the gate of the EPROM transistor.
EPROMS are available in several varieties. In the traditional and most basic form, EPROMs are programmed electrically and erased by exposure to ultraviolet light. The EPROMs can be referred to as ultraviolet erasable programmable read-only memories ("UVEPROMs"). UVEPROMs are programmed by running a high current between the drain and the source of the UVEPROM transistor while applying a positive potential to the gate. The positive potential on the gate attracts energetic ("hot") electrons from the drain-to-source current, which jump onto the floating gate in an attempt to reach the gate and become trapped on the floating gate.
Another form of EPROM is the electrically erasable programmable read-only memory ("EEPROM" or "E.sup.2 PROM"). EEPROMs are programmed and erased electrically using a phenomenon known as Fowler-Nordheim tunneling.
Still another form of EPROM is "Flash EPROM," which is programmed using hot electrons like traditional EPROMs (i.e., UVEPROMs) and electrically erased using Fowler-Nordheim tunneling like an EEPROM. Both Flash EPROMs and EEPROMs-which can be erased in a "flash" or bulk mode in which all cells in an array can be erased simultaneously using Fowler-Nordheim tunneling-will be referred to hereinafter as "Flash cells" or "Flash devices."
Both UVEPROMs and EEPROMs have been used for both memory applications and programmable logic applications. One obstacle to using Flash devices is the phenomenon of overerasure. Overerasure is the result of continuing the Fowler-Nordheim erase process too long, so that too much charge is removed from the floating gate, with the result that the Flash device goes into depletion mode, in which it is always conducting (unless the gate-to-source voltage goes negative).
In a programmable logic device ("PLD") or memory chip in which there is an overerased Flash transistor, the leakage current resulting from the depletion mode operation of that transistor can interfere with accurate reading of the states of neighboring cells in the array. This can be cured by having in each cell a second "select" transistor, allowing the selection or deselection of a particular device for reading. Many flash memory applications employ such select transistors. However, in logic applications, the use of such a transistor consumes considerable space on the chip and impacts array speed.
One solution frequently employed to prevent overerasure of flash devices is to use an "intelligent" erasing algorithm in which the device is incrementally erased in small amounts and then verified to determine whether the memory cell threshold has shifted the desired amount, but not so far as to go into depletion mode. However, such a technique can be time-consuming and adds to programming complexity.
In commonly-assigned U.S. Pat. No. 5,138,576, hereby incorporated by reference in its entirety, a method and apparatus are disclosed for erasing individual cells in an array of electrically erasable EPROM cells. This is accomplished by connecting a select transistor to each row in the array and a switch to each column. An individual cell is selected to be erased by activating the appropriate switch and select transistor. When the memory cell is erased, a sense amplifier disconnects that cell from its erase line by controlling a stop transistor coupled to the column. While this circuit prevents overerasure, it still requires use of several additional circuit elements, such as the sense amplifier, switches and select transistor to isolate individual cells.
Accordingly, it would be desirable to erase an array of memory cells while preventing overerasure without impacting overall performance by using several additional circuit elements or the time-consuming intelligent erasure algorithm.